1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same and, more particularly, to optimization in a capacitance component of a MOS transistor formed on a single pellet, e.g., an RF output transistor.
2. Description of the Related Art
Conventionally, along with the developments in lower-breakdown-voltage, higher-frequency devices, a semiconductor device such as an RF high-output MOSFET used in an RF amplifier circuit has been required for higher performance due to the scaling rule. Micropatterning for elements is thus required, which increases the effects of size variations, and the effect on capacitance components in the device.
FIG. 19 is a plan view showing a semiconductor device with a MOS transistor formed on a single pellet according to a prior art, FIG. 20 is a sectional view of the MOS transistor taken along the line of XX—XX, and FIG. 21 is a circuit diagram of the MOS transistor shown in FIG. 20.
As shown in FIGS. 19 and 20, n-type impurity diffusion regions are formed in the upper surface region of a p-type semiconductor substrate 1 formed from a silicon semiconductor or the like. A source region 2 and drain region 3 are formed in the respective n-type impurity diffusion regions to oppose each other. The source region 2 is electrically connected to a p+-type impurity diffusion region 10 which is electrically connected to source electrodes (S) 8. The drain region 3 is contiguous to an n+-type impurity diffusion region 11 which is electrically connected to a drain electrode (D) 9. A gate region 5 is formed above a region between the source region 2 and drain region 3 through a gate insulating film 4. The gate insulating film 4 and gate region 5 are covered with an insulating film 6 formed from a silicon oxide film or the like.
A gate electrode (G) 7 made of aluminum or the like and the drain electrode 9 made of aluminum or the like are formed on the insulating film 6. The source electrodes 8 made of aluminum of the like are formed on the lower surface of the semiconductor substrate 1 and a portion of an element region close to the gate region 5 on the major surface of the semiconductor substrate 1. The gate electrode 7 is not formed immediately above the gate region 5 arranged in the element region but is formed at a position two-dimensionally spaced apart from the gate region 5 on the upper surface of the semiconductor substrate 1. A gate bonding portion 12 which is made of aluminum or the like and connects to an external circuit is additionally formed on the gate electrode 7. The drain electrodes 9 are respectively formed on the drain region 3 arranged in the element region and along a two-dimensionally separated position on the upper surface of the semiconductor substrate 1. A drain bonding portion 13 which is made of aluminum or the like and connects to an external circuit is additionally formed on the drain electrode 9.
As shown in FIG. 21, parasitic capacitances C3 and C4 are formed in a MOS transistor formed in the semiconductor substrate 1 described above. The parasitic capacitances C3 and C4 are electrostatic capacitances generated between wirings or electrodes, which are inevitably generated in element formation.
In order to obtain a high output, the RF high-output MOS transistor requires matching circuits in input/output units. However, a capacitance component generated in a transistor varies according to the position or size of the wiring, electrode, or the like. This variation affects the matching circuits. As a result, a mismatch occurs in each matching circuit, and this makes it difficult to obtain a high output. To prevent this, an external capacitor is conventionally connected to the MOS transistor when necessary to adjust the above-described variation. However, formation of this capacitor requires a complicated manufacturing process, and accurate adjustment for the capacitance is difficult.